In an active matrix with integrated peripheral control circuits, the pixel electrodes and the associated switching transistors for the image points, as well as the control circuits for the rows and columns of pixel electrodes, are made at the same time on the same substrate.
The row control circuits, commonly called “row drivers” in the technical literature, make it possible, with each new video frame to be displayed, to apply the row selection signals one after the other along a direction of scan of the rows of the screen.
These control circuits comprise for this purpose one or more shift registers in series, each output stage of the registers delivering the selection signal for a given matrix row.
Patent application EP 0815 562 discloses an advantageously simple structure with so-called “bootstrap” autoboost capacitors and transistors for making the stages of a shift register, which makes it possible to profit from a beneficial voltage boost effect, so as to provide the high voltage level expected on the rows of the matrix, while limiting the stress on the transistors of the stage. It makes it possible to use the same technology of transistors for the register and for the active matrix, notably thin-film transistors having thin layers of hydrogenated amorphous silicon. This structure makes it possible to work with control signals at the input of each stage, having a lower amplitude than that of the output signals of the register, limiting the stress on the gates of the transistors of the stage. Furthermore the structure ensures that the transistors of the unselected stages are turned off. In this way the reliability of these shift registers is improved. This shift register structure is biphase, that is to say it is driven by two complementary clocks, whose roles reverse between each stage. This makes it possible to ensure a very low duty ratio of the transistors, and therefore to ensure substantially the same lifetime for the transistors of the shift register as for the switching transistors of the active matrix.
This structure is recalled hereinafter, with reference to FIGS. 1a and 1b, derived from FIG. 3 of the aforesaid European application.
The nth row of the active matrix is denoted R(n), and the stage of the shift register 1 controlling this row R(n) is denoted En.
The stage En is supplied by a negative source V− fed via a power supply bus and sequenced by two complementary clock signals Ck1 and Ck2. It is connected at inputs to a previous row R(n−1) and to a following row R(n+1) of the matrix. The voltage V− is typically equal to the turn-off voltage Vgoff of the transistors.
The stage En (FIG. 1a) comprises four transistors T1, T2, T3 and T4, and two capacitors C1 and C2.
The transistors T1 and T2 are connected in series, between the previous row R(n) and the potential V−. The transistor T1 is mounted diode fashion, its gate being connected to its drain, and connected to the previous row R(n−1). The gate of the transistor T2 is connected to the following row R(n+1). The internal node Pn corresponds to the series connection node of the two transistors T1 and T2, and drives the gate G of the transistor T3. The transistor T1 mounted diode fashion has a function of precharging this internal node Pn.
The transistors T3 and T4 are mounted in series, between a first clock signal, in the example Ck2, and the potential V−. The transistor T3 is the control transistor of the stage, or “drive” transistor, that is to say that which controls the output node Sn connected to the selection row R(n). It is controlled on its gate by the potential at the internal node Pn of the stage. The gate of the transistor T4 is connected to the following row R(n+1).
The capacitor C1 is driven by a clock signal, in the example Ck1, and connected to the internal node Pn which drives the gate of the drive transistor T3. This capacitor C1 has only a compensation function, to compensate for the gate-drain stray capacitance of the drive transistor T3 during the switching of the signals Ck1 and Ck2.
The capacitor C2 is connected between the internal node Pn and the output node Sn connected to the row R(n).
The roles of the clock signals Ck1 and Ck2 are interchanged from one stage to another: in stage En+1 for example, it is the capacitor C1 which receives the clock signal Ck2 and the drive transistor T3 which receives the signal Ck1.
FIG. 1b schematically illustrates a shift register 1 comprising 481 stages. The first stage E1 receives as input signal applied to the gate of the precharge transistor T1, the signal IN which provides the row selection pulse corresponding to a new video frame.
This signal IN propagates from row to row, in the row sequence, via the stages E1, E2, . . . En, . . . E481, so that the rows R(1) to R(481) are each selected one after the other.
The manner of operation of a stage of this register will now be briefly explained, with reference to stage En detailed in FIG. 1a and to the time chart of FIG. 3.
The clock signals Ck1 and Ck2 are complementary, i.e. in phase opposition. Typically the high level of these signals is the level Vgon (for example 26 volts), and the low level (V−), typically the level Vgoff (for example—7 volts).
The selection of the row R(n) is made when the output node Sn of stage En is raised to the high level Vgon.
Let us assume that row R(n) is selected during the row time tn. Row R(n−1) was selected over the previous row time tn−1.
During the row time tn−1, the clock signals Ck1 and Ck2 are respectively in the high state Vgon and in the low state Vgoff and the output node Sn−1 is at Vgon.
During this row time, the transistor T1 (mounted diode fashion) of stage En charges the internal node Pn for gate control of the drive transistor T3, to the level Vgon−VtT1 of the output node Sn−1 of the previous stage (FIG. 3), where VtT1 is the threshold voltage of the transistor T1.
At time tn, the state of the clock signals Ck1 and Ck2 reverses.
With the clock signal Ck2 returning to the low state Vgoff, the output node Sn−1 drop backs to Vgoff: row R(n−1) is deselected. The output node Sn−1 returns to Vgoff and the transistor T1 of stage En turns off.
The clock signal Ck2 applied to the drive transistor T3 thus passes to the high state Vgon−VtT1: the drive transistor T3 passes to the on state. The voltage at the internal node Pn, which controls the gate of the drive transistor T3, rises with the source voltage (node Sn) of the transistor T3 through the so-called “bootstrap” effect through the capacitor C2, thereby maintaining the drive transistor T3 in the on state during the row time tn.
The transistors T2 and T4 of stage En−1 then turn on, since their gates are taken to Vgon by the output node Sn of stage En, thereby pulling the internal node Pn−1 and the output node Sn−1 of stage En−1 to Vgoff: row R(n−1) is deselected and the bootstrap capacitor C2 discharged.
When Ck1 rises back to Vgon and Ck2 drops back to Vgoff, the sequence is repeated for the following stage, replacing n−1 by n, n by n+1 and Ck1 by Ck2 and vice versa. Thus, with each edge of the clocks Ck1 and Ck2, there is propagation in the shift register of a row selection pulse.
The scan sequence for the rows of the matrix begins with the activation of the signal IN, which ensures the precharging of the internal node P1 of the first stage.
For the last stage, a signal R-last must be provided, so as to discharge the internal node P481 of the last stage, marking the end of the selection of the associated row R(481) (cf FIG. 1b).
For each video frame to be displayed corresponding to a frame time, each of the rows R(1) to R(481) of the matrix is thus successively selected by the associated stage, each during a row time.
A corresponding manner of operation is illustrated by the time chart of FIG. 2.
When a stage En is not selected, the two transistors in series T1 and T2 pull some current of the previous row R(n−1) toward Vgoff. The two transistors then have lower gate-source voltages than their threshold voltage, and their channel current is an exponential function of these voltages. As a result of this arrangement, the voltage at the internal node Pn is about 1 volt lower than its source voltage: the transistor T3 is in the off state. Thus, when a stage of the shift register is not selected, its transistors have their gate at a lower voltage than their threshold voltage, hence minimized transistor fatigue.
This shift register according to the prior art, or variants of this register which use the basic structure which has just been described, are much used. The transistors of the register are generally made via the same technology as those of the active matrix.
A very troublesome effect has, however, been observed on active-matrix screens furnished with such a shift register for controlling the rows, namely a reverse scan, from the top to the bottom, which gives rise to double writing of the video during the frame time, giving a mirror effect visual impression of the image to be displayed.
More precisely, it may be noted that, whereas the image is displayed from the top to the bottom, and the top of the screen is displayed normally, in parallel, the image is written from the bottom to the top: it is thus possible to observe an inverted partial display at the bottom of the screen of the image which is displayed at the top of the screen, with a join close to the middle of the screen. This leads to this mirror effect impression observed on the screen, between the top and the bottom.
It has been possible to discover that this double writing is in fact initiated by the presence, under certain conditions, of charges in the stages of the shift register, and more particularly of charges on the so-called bootstrap capacitor C2. It has been possible to demonstrate that the effect of these charges is to cause a scan of the rows in the reverse direction, activated by the discharge signal R-last for the last stage of the shift register. Once this reverse scan starts, it furthermore has the feature of being self-sustaining, so that the mirror effect is observed continually, from frame to frame.
In a more detailed manner, it has been possible to demonstrate that this mirror effect can be triggered by the activation of the signal R-last when, in the last stages of the register, bootstrap capacitors C2 are charged to a level such that the drive transistors T3 of these stages become biased to the conduction threshold, in which they have a linear behavior.
Let us consider for example the last three stages E479, E480, E481, with the transistors T3 of stages E479 and E481 being driven by the clock signal Ck2 and the transistor T3 of stage E480 being driven by the clock signal Ck1.
The clock signal Ck2 being in the high state Vgon, if the capacitors C2 of these stages are precharged, the transistors T3 of stages E479 and E481 will follow the state of the clock signal Ck2. So the precharge transistor T1 and the transistor T2 of stage E480 are on, passing a current i between Ck2 and V−: the potential at the internal node P480 of this stage thus becomes steady at an intermediate value between Vgon (high state of Ck2) and V−.
The same phenomenon occurs for all the even rows which are flanked by two odd rows under the same conditions.
The sum of these currents i which flow in the even stages at this instant causes the potential on the power supply bus V− to rise on account of the impedance of this bus. Under these conditions, this yields a potential V− whose value varies as a function of the rank of the stage, in practice between −7 volts (Vgoff) for the first stage and nearly +1 volt for the last stage E481: the voltage level V− climbs toward the bottom of the screen.
The effect of this climb in the voltage V− at the bottom of the screen is to make the transistors T2 conduct less, and therefore promotes the rise in the potential of the internal node of the stages concerned.
Then we have even stages, which are kept incompletely precharged because of the divider bridge (T1,T2), during the active state at Vgon of the clock signal Ck2. The transistors T3 of these stages are thus slightly passing, sufficiently to sustain the precharge of the capacitors C2 of the odd stages; and the capacitors of these odd stages are more precharged than that of the even stages: the transistors T3 are almost saturated, and that of the last stage is in fact completely saturated.
In practice, under certain conditions, the following may thus be observed:
the propagation of a selection pulse of full amplitude on even rows of the screen: typically for example the video of row 2 will be written on row 472, the video of row 4 will be written on row 470, etc: this is the mirror effect.
a progressive filling in the bottom of the screen of the stages of the register caused by this pulse, which regenerates the starting conditions of the mirror effect observed, and sustains it.
In practice, this mirror effect can only be eliminated with the use of a specific initialization procedure triggered when the screen starts up, so as to obtain the discharging of each of the bootstrap capacitors of the stages of the register. This procedure consists in the application, during the screen initialization phase, of specific addressing conditions, which may be for example:
maintaining the signals Ck1, Ck2 at the level Vgoff for a specific time, typically of the order of a second, so as to discharge the so-called bootstrap capacitors C2; or
forcing the signal R-last to the high state for a specific time, typically for about ten frames.
In the invention, another technical solution to the mirror effect problem has been found, in bootstrap capacitor discharge means integrated into each of the stages of the register.
The invention thus relates to a shift register integrated on the active-matrix substrate of a flat screen, for controlling selection rows for image points of the screen, comprising a plurality of stages in cascade, each stage being driven by first and second complementary clock signals and providing a row selection signal on an output node, and each stage comprising between an internal node and said output node (Sn):
a first and a second transistor connected in series between an output node of a previous stage, or a mode receiving for an input signal of the register, and a negative power supply bus, the midpoint of connection between said first and second transistors being said internal node of the stage,
a third and a fourth transistor connected in series between a clock signal from among the first and the second clock signals, and a negative power supply bus, the gate of said third transistor being connected to said internal node, the midpoint of connection between said third and fourth transistors being said output node,
and said second and fourth transistors being controlled on their gate by the output signal of a following stage, or of a discharge control signal in the case of the last stage of the register, and
a first capacitor connected between the other clock signal and said internal node, and a second capacitor connected between said internal node and said output node,
each stage comprising a discharge circuit for said second capacitor,
wherein said discharge circuit is activated by an activation signal which is the discharge control signal (R-last) of the last stage, this signal (R-last) being forced to the active state when the screen starts up.
In a variant, the signal for activating the discharge circuit for the stage of rank n is provided by the output node of a stage of previous but not immediately previous rank, advantageously of rank n−2.
According to an embodiment of the invention, said discharge circuit consist of a transistor connected in parallel with said second capacitor.
According to another embodiment of the invention, said discharge circuit consist of a first transistor connected in parallel between the internal node and said negative power supply bus, and a second transistor connected in parallel between the output node and said negative power supply bus.
The invention applies to active-matrix flat screens, in particular to liquid crystal screens.